computer-architecture-mcqs - Set (1)

Correct Answer: Orange && Worng Answer: Red

1. Which of the following is lowest in memory hierarchy?

  • (A). Cache memory
  • (B). Secondary memory
  • (C). Register
  • (D). RAM
    • View Answer

    Explanation: Not Avilable

    2. Cache memory acts between-

  • (A). CPU and RAM
  • (B). RAM and ROM
  • (C). CPU and Hard disk
  • (D). None of these
    • View Answer

    Explanation: Not Avilable

    3. The technique where the controller is given complete access to main memory is –

  • (A). Cycle stealing
  • (B). Memory stealing
  • (C). Burst mode
  • (D). None of these
    • View Answer

    Explanation: Not Avilable

    4. Interrupts initiated by an instruction is called as-

  • (A). internal
  • (B). extenal
  • (C). hardware
  • (D). software
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    Explanation: Not Avilable

    5. Which memory is used to copy instruction or data currently used by CPU ?

  • (A). Main memory
  • (B). Secondary memory
  • (C). Cache memory
  • (D). None of these
    • View Answer

    Explanation: Not Avilable

    6. Which register holds the current instruction to be executed ?

  • (A). Instruction register
  • (B). Program register
  • (C). Control register
  • (D). None of these
    • View Answer

    Explanation: Not Avilable

    7. In stack organization address register is known as the :

  • (A). Memory stack
  • (B). Stack pointer
  • (C). Push operation
  • (D). Pop operation
    • View Answer

    Explanation: Not Avilable

    8. In which addressing the simplest address mode where an operand is fetched from memory is ______

  • (A). Immediate addressing
  • (B). Direct addressing
  • (C). Register addressing
  • (D). None of these
    • View Answer

    Explanation: Not Avilable

    9. ______ are numbers and encoded characters generally used as operands.

  • (A). Input
  • (B). Data
  • (C). Information
  • (D). Stored values
    • View Answer

    Explanation: Not Avilable

    10. ______ bus structure is usually used to connect I/O devices.

  • (A). Single bus
  • (B). Multiple bus
  • (C). Star bus
  • (D). RAM bus
    • View Answer

    Explanation: Not Avilable

    11. Cycle stealing is used in ______

  • (A). DMA
  • (B). Pipelining
  • (C). Register
  • (D). None of these
    • View Answer

    Explanation: Not Avilable

    12. DMA stands for ______

  • (A). Direct Memory Address
  • (B). Direct Main Address
  • (C). Direct Memory Access
  • (D). Device Memory Access
    • View Answer

    Explanation: Not Avilable

    13. Combinational circuit depends only on

  • (A). Present input
  • (B). Past output
  • (C). Both present and past
  • (D). None of the above
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    Explanation: Not Avilable

    14. The addressing mode where address of DATA is stored in CPU register ?

  • (A). Register direct
  • (B). Register indirect
  • (C). Immediate
  • (D). None of these
    • View Answer

    Explanation: Not Avilable

    15. CISC stands for –

  • (A). Control instruction set content
  • (B). Control instruction set computer
  • (C). Complex instruction set conversion
  • (D). Complex instruction set computer
    • View Answer

    Explanation: Not Avilable

    16. Which of the following is responsible for co-ordinating various operations using timing signals ?

  • (A). ALU
  • (B). CU
  • (C). Input unit
  • (D). Output unit
    • View Answer

    Explanation: Not Avilable

    17. The correspondence between the main memory blocks and those in the chache is specified by –

  • (A). Mapping function
  • (B). Replacement algorithm
  • (C). Nitrate
  • (D). Miss penalty
    • View Answer

    Explanation: Not Avilable

    18. The register that keeps track of the address of the next instruction to be executed is ______

  • (A). AC
  • (B). PC
  • (C). IR
  • (D). AR
    • View Answer

    Explanation: Not Avilable

    19. What is stored in the stack pointer ?

  • (A). Operations
  • (B). Addressing method
  • (C). Stack data values
  • (D). Address of top item
    • View Answer

    Explanation: Not Avilable

    20. Multiplexer consist of how many number of ouputs?

  • (A). Only one
  • (B). No output
  • (C). Two output
  • (D). Four output
    • View Answer

    Explanation: Not Avilable

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